Discovered 19h ago

ASIC Engineering Design Verification Leader (SystemVerilog, Python, C and UVM |8-12 years| Pune)

Cisco•Workday

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LocationPune, India

Work Modeonsite

Experience8+ yrs

CompensationNot disclosed

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Required Skills & Technology Stack

SystemVerilogUVMRTL DesignPythonDftCiscoASICSynopsysEthernetFPGARTLMachine LearningCadence

About the Role

Meet the Team Cisco’s Client Optics Group (COG) designs & delivers the high-speed optical transceivers, and platforms that power Cisco's core data center networking solutions. We specialize in the design and integration of cutting-edge IM/DD optics and silicon photonic platforms that enable customers to deploy industry-leading optical technologies within data center with unprecedented speed,…

This role in context

Python is one of the skills this role asks for. It appears in 39,284 active tech jobs in India (33.2% of those we track). This posting asks for 8+ years. 48% of Python jobs that state experience ask for 5–8 years. Pune accounts for 13% of Python jobs. 13% of Python jobs are remote; this one is onsite.

Based on active listings from the last 30 days. See the full Python job data →