Discovered 24d ago

Design Verification Engineer - System Verilog

Neurealm•Hirist

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LocationBangalore, Cochin/Kochi, Chennai, Pune

Work Modeonsite

Experience5+ yrs

CompensationNot disclosed

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Required Skills & Technology Stack

SystemVerilogUVMVerificationAMBAARMDesign VerificationVerilogPythonperlLinuxpcieExpressethernetrtl

About the Role

Design Verification Engineer : Experience : 5 - 8 Years Location : Bangalore / Kochi / Chennai / Pune Job Type : Full-time About the Role : We are looking for a skilled Design Verification Engineer with hands-on experience in live semiconductor/SoC verification projects. The ideal candidate should have strong expertise in SystemVerilog and UVM, functional verification methodologies, protocol…

This role in context

Python is one of the skills this role asks for. It appears in 39,090 active tech jobs in India (33.3% of those we track). This posting asks for 5+ years. 48% of Python jobs that state experience ask for 5–8 years. Pune accounts for 13% of Python jobs. 13% of Python jobs are remote; this one is onsite.

Based on active listings from the last 30 days. See the full Python job data →