Discovered 3mo ago

ASIC RTL Design Engineer

Einfochips•Hirist

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LocationAhmedabad, Bangalore, Noida, Hyderabad, Pune, Chennai

Work Modeonsite

Experience5+ yrs

CompensationNot disclosed

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Required Skills & Technology Stack

ASICRTL DesignVerilogSystemVerilogSoCDFTPhysical DesignAMBAPythonperlstartlsynthesis

About the Role

ASIC RTL Design Engineer Experience : 5 to 12 Years Location : Bangalore ,Hyderabad , Pune , Noida , Ahmedabad , Chennai Role Summary : We are seeking a hands-on ASIC RTL Design Engineer with strong expertise in RTL design and SoC development. The ideal candidate should have experience in designing high-quality, synthesizable RTL for complex ASIC/SoC projects. Key Responsibilities : - Develop RTL…

This role in context

Python is one of the skills this role asks for. It appears in 39,658 active tech jobs in India (33.1% of those we track). This posting asks for 5+ years. 48% of Python jobs that state experience ask for 5–8 years. Hyderabad accounts for 16% of Python jobs. 13% of Python jobs are remote; this one is onsite.

Based on active listings from the last 30 days. See the full Python job data →