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Discovered 4d ago
HCLTech

ASIC SOC Design Verification - System Verilog;UVM

HCLTech•Linkedin
LocationGreater Bengaluru Area
Work Modeonsite
Experience6+ yrs
Compensation~₹14–24 LPA

Required Skills & Technology Stack

VHDLperluvmverilogasicPython

About the Role

Experience: 6–15 Years Locations: Chennai | Bangalore | Hyderabad Department: Semiconductor / ASIC / SoC Engineering 🌟 About the Role HCLTech is looking for a highly accomplished Design Verification Engineer (DV) to lead verification for our most critical ASIC and SoC programs . This is a senior technical leadership role that demands deep expertise in verification methodologies and a proven…

This role in context

Python is one of the skills this role asks for. It appears in 16,203 active tech jobs in India (29.6% of those we track). This posting asks for 6+ years. 49% of Python jobs that state experience ask for 5–8 years. Bengaluru accounts for 35% of Python jobs. 15% of Python jobs are remote; this one is onsite.

Based on active listings from the last 30 days. See the full Python job data →

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