Discovered 1d ago

UVM ASIC Design Verification Engineer

Blue Fish Technologies•Linkedin

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LocationHyderabad, Telangana, India

Work Modeonsite

Experience5+ yrs

Estimated compensation~₹14–24 LPA

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Required Skills & Technology Stack

uvmverilogPythonasicethernet

About the Role

Job Title – UVM ASIC Design Verification Engineer Experience: 5- 15Year(s) Job Type: Full-time Location: Hyderabad, India Job Description: ● B.Tech/M.Tech in Electronics & Communication Engg. ● Experience - Minimum 5+ years ● Experience with complex ASIC projects, with demonstrated mastery of successful verification from test planning till tapeout ● Strong background in System Verilog…

This role in context

Python is one of the skills this role asks for. It appears in 19,958 active tech jobs in India (29.4% of those we track). This posting asks for 5+ years. 50% of Python jobs that state experience ask for 5–8 years. Hyderabad accounts for 16% of Python jobs. 14% of Python jobs are remote; this one is onsite.

Based on active listings from the last 30 days. See the full Python job data →