Discovered 7d ago

Lead RTL Design Engineer

ACL Digital•Linkedin

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LocationChennai, Tamil Nadu, India

Work Modeonsite

Experience6+ yrs

Compensation~₹14–24 LPA

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Required Skills & Technology Stack

Pythonsynthesisrtl designVHDLrtlverilogasic

About the Role

Lead RTL Design Engineer (ASIC) Location: Chennai, Tamil Nadu Experience: 6 to 9 Years Job Description 6 to 9 Years of experience in Synthesis, Constraints and interface timing Challenges. Good knowledge of Power is preferable. Strong Domain Knowledge on RTL Design, implementation, and Timing analysis. Experience with RTL coding using Verilog/VHDL/System Verilog. Experience in micro-architecture…

This role in context

Python is one of the skills this role asks for. It appears in 16,203 active tech jobs in India (29.6% of those we track). This posting asks for 6+ years. 49% of Python jobs that state experience ask for 5–8 years. Chennai accounts for 9% of Python jobs. 15% of Python jobs are remote; this one is onsite.

Based on active listings from the last 30 days. See the full Python job data →