Senior Principal Frontend RTL Engineer

We are looking for a PCIe Sub-system Front-end RTL lead for next generation chiplet based SoCs for High-performance Compute and AI silicon . What You’ll Do Own the PCIe subsystem microarchitecture from the PHY interface through the MAC and Transaction Layer, defining the internal block boundaries, data paths, and control interfaces. Lead the integration of third-party PCIe controller and PHY hard…