Design Verification Lead

Experience:10+ years Location:Hyderabad • Familiarity with SoCs and boot flow would be useful. • SV UVM based TB environment setup, usage of UVM VIPs. • Developing UVM sequences, tests, TB bring up and sanity regressions. • Familiarity with Software development flow including assembly and C is beneficial. • Knowledge of system-level architecture including buses like AXI/CHI/ACE5, bridges, memory…