Application Specific Integrated Circuit Design Engineer

Role - RTL design Experience - 5+ Years Location - Bangalore, Kochi and Hyderabad Digital Design • 5 plus Strong RTL design experience using Verilog/SystemVerilog. • Good understanding of: o FSM design o Clock-domain crossing (CDC) o Reset-domain crossing (RDC) o Timing concepts o Low-power design fundamentals • Experience with synthesis and static timing analysis concepts. Mixed-Signal…