Sr. Design Verification Engineer_Pune

5+ Years Experience in System Verilog and UVM methodology Hands-on expertise in high-speed interface protocols (PCIe / CXL/UCIE/USB / DDR / Ethernet / AXI, etc.) Good understanding of verification concepts, coverage, assertions, and debugging Experience with simulation tools (VCS, Questa, Xcelium, etc.) Strong analytical & problem-solving skills Share your updated resume:…