RTL SOC integration

• Authoring and owning 3rd party IP integration. • Multi-domain CDC analysis • ASEP 8-port interface: 32-to-16-bit width adaptation, async FIFO design, stype routing, SOP/EOP framing • APB/SOC slave bus bridge; register map ownership; RGGEN-based CSR methodology • System Verilog (RTL and assertions), lint (Cadence HAL/SpyGlass), linting closure, cadence CDC tool • Working knowledge of ASA-ML DLL,…