SOC Verification Engineer

We are looking for a SOC Design Verification (DV) Engineer with 3+ years of experience in SoC/ASIC verification and strong SV and UVM skills. Location: Bangalore Experience: 3+ Years Key Responsibilities: Develop and execute UVM/SystemVerilog based verification environments. Create testbenches, test plans, assertions, and functional coverage. Perform block, subsystem, and SoC-level…