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Discovered 1d ago
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Senior DFT (Design for Testability) Engineer

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LocationGreater Bengaluru Area
Work Modeonsite
Experience5+ yrs
Compensation~₹14–24 LPA

Required Skills & Technology Stack

cadencephysical designasicvlsidftstasynopsyssynthesisperlrtl

About the Role

Job Title: Senior DFT Engineer Experience Level: 5+ Years Work Location: Bangalore, India Domain: VLSI / Semiconductor / ASIC Design Employment Type: Full-Time Position Overview: We are seeking an experienced and self-driven Senior DFT (Design for Testability) Engineer with 5+ years of hands-on experience to lead and execute block-level and chip-level DFT architecture, implementation, pattern…

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