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Discovered 1d ago
C
Multiple Post Silicon Electrical Validation Engineer roles (grades T2 to T5) at Cadence Bangalore
Cadence•Linkedin
LocationBengaluru, Karnataka, India
Work Modeonsite
Experience2+ yrs
Compensation~₹8–14 LPA
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Required Skills & Technology Stack
C++c/c++usbcadencebertverilogrtlethernetpcbFPGAPythonpcie
About the Role
There are multiple openings for Post Silicon Electrical Validation Engineer roles (grades T2 to T5, ie, Test Engineer II to Senior Principal Test Engineer/Senior Test Engineering Manager) in High Speed SERDES Physical Layer Electrical Validation Domain at Cadence Design Systems, Bangalore. The roles are intended for candidates with direct experience in this domain in the range 2 years to 15 years…
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